Yield Modeling of Bipolar Integrated Circuits

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Abstract

<jats:p> The equation correlating yield, chip-size and defect density is reanalysed with respect to its applicability in a production environment. This implies that most of the information necessary for a statistical evaluation is derived from electrical measurements at wafer probe stations in order to obtain the required amount of data. The advantages of test structures and the importance of some layout parameters are emphasized. The procedure discussed is applied to modern bipolar technology. Two IC's (memory, random logic) are used to demonstrate the influence of certain defects on the total yield. </jats:p>

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