New device technologies for 5 V-only 4 Mb EEPROM with NAND structure cell

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Novel device technologies for a 5-V-only EEPROM (electrically erasable programmable read-only memory) with a NAND structure cell are described. By applying half of the programming voltage to unselected bit lines and a successive programming sequence, the NAND structure cell keeps a wide threshold margin. A high-voltage CMOS process realizes reliable programming characteristics. The reliability of the cell has been confirmed experimentally. Using 1.0- mu m design rules, the unit cell area per bit is 12.9- mu m/sup 2/, which is small enough to realize a 4-Mb EEPROM. >

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