Highly area efficient and cost effective double stacked S/sup 3/(stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM
収録刊行物
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- IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.
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IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. 265-268,
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