Implantation‐based passivating contacts for crystalline silicon front/rear contacted solar cells

  • Gianluca Limodio
    Photovoltaic Material and Devices Group Delft University of Technology PO Box 5031 2600 GA Delft The Netherlands
  • Guangtao Yang
    Photovoltaic Material and Devices Group Delft University of Technology PO Box 5031 2600 GA Delft The Netherlands
  • Yvar De Groot
    Photovoltaic Material and Devices Group Delft University of Technology PO Box 5031 2600 GA Delft The Netherlands
  • Paul Procel
    Photovoltaic Material and Devices Group Delft University of Technology PO Box 5031 2600 GA Delft The Netherlands
  • Luana Mazzarella
    Photovoltaic Material and Devices Group Delft University of Technology PO Box 5031 2600 GA Delft The Netherlands
  • Arthur W. Weber
    Photovoltaic Material and Devices Group Delft University of Technology PO Box 5031 2600 GA Delft The Netherlands
  • Olindo Isabella
    Photovoltaic Material and Devices Group Delft University of Technology PO Box 5031 2600 GA Delft The Netherlands
  • Miro Zeman
    Photovoltaic Material and Devices Group Delft University of Technology PO Box 5031 2600 GA Delft The Netherlands

抄録

<jats:title>Abstract</jats:title><jats:p>In this work, we develop SiO<jats:sub>x</jats:sub>/poly‐Si carrier‐selective contacts grown by low‐pressure chemical vapor deposition and boron or phosphorus doped by ion implantation. We investigate their passivation properties on symmetric structures while varying the thickness of poly‐Si in a wide range (20‐250 nm). Dose and energy of implantation as well as temperature and time of annealing were optimized, achieving implied open‐circuit voltage well above 700 mV for electron‐selective contacts regardless the poly‐Si layer thickness. In case of hole‐selective contacts, the passivation quality decreases by thinning the poly‐Si layer. For both poly‐Si doping types, forming gas annealing helps to augment the passivation quality. The optimized doped poly‐Si layers are then implemented in c‐Si solar cells featuring SiO<jats:sub>2</jats:sub>/poly‐Si contacts with different polarities on both front and rear sides in a lean manufacturing process free from transparent conductive oxide (TCO). At cell level, open‐circuit voltage degrades when thinner p‐type poly‐Si layer is employed, while a consistent gain in short circuit current is measured when front poly‐Si thickness is thinned down from 250 to 35 nm (up to +4 mA/cm<jats:sup>2</jats:sup>). We circumvent this limitation by decoupling front and rear layer thickness obtaining, on one hand, reasonably high current (J<jats:sub>SC‐EQE</jats:sub> = 38.2 mA/cm<jats:sup>2</jats:sup>) and, on the other hand, relatively high V<jats:sub>OC</jats:sub> of approximately 690 mV. The best TCO‐free device using Ti‐seeded Cu‐plated front contact exhibits a fill factor of 75.2% and conversion efficiency of 19.6%.</jats:p>

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