A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit
書誌事項
- 公開日
- 2002-12
- 権利情報
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- https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html
- DOI
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- 10.1109/jssc.2002.804342
- 公開者
- Institute of Electrical and Electronics Engineers (IEEE)
この論文をさがす
収録刊行物
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- IEEE Journal of Solid-State Circuits
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IEEE Journal of Solid-State Circuits 37 (12), 1822-1830, 2002-12
Institute of Electrical and Electronics Engineers (IEEE)