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- R. Kotlyar
- Technology CAD, Intel Corporation, Hillsboro, Oregon 97124
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- B. Obradovic
- Technology CAD, Intel Corporation, Hillsboro, Oregon 97124
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- P. Matagne
- Technology CAD, Intel Corporation, Hillsboro, Oregon 97124
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- M. Stettler
- Technology CAD, Intel Corporation, Hillsboro, Oregon 97124
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- M. D. Giles
- Technology CAD, Intel Corporation, Hillsboro, Oregon 97124
書誌事項
- 公開日
- 2004-06-21
- DOI
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- 10.1063/1.1762695
- 公開者
- AIP Publishing
この論文をさがす
説明
<jats:p>The technologically important question of whether the reduced density of electron states (DOS) for scattering in one-dimensional (1D) wire transport devices gives an advantage over the planar metal–oxide–semiconductor field-effect-transistor (MOSFET) for electron mobility is assessed by simulations. We self-consistently solve the Schrödinger–Poisson equations to calculate phonon-limited electron mobility in a multisubband cylindrical Si gated wire. We find that the benefit of reduced 1D DOS is offset by an increased phonon scattering rate due to increased electron–phonon wave function overlap and results in a degraded mobility in narrow wires. The applied gate bias voltage and the wire size control the transition from wire geometry to surface field-dominated confinement. The size scale for this 1D to two-dimensional (2D) transition is also found to be surprisingly small: A wire with a 75 A radius has an essentially 2D DOS and has a 2D mobility that is degraded from the planar (100) MOSFET due to the anisotropy of the inversion mobility in different Si crystallographic planes.</jats:p>
収録刊行物
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- Applied Physics Letters
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Applied Physics Letters 84 (25), 5270-5272, 2004-06-21
AIP Publishing