An efficient and precise design method to optimize device areas in mismatch and flicker-noise sensitive analog circuits
書誌事項
- DOI
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- 10.1109/icecs.2001.957687
- 公開者
- IEEE
収録刊行物
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- ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)
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ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) 1 107-111,
IEEE
