A $720\mu \mathrm{W}$ 77.93dB SNDR $\Delta\Sigma \text{AD}$ Modulator Using Dynamic Analog Components With Simplified Operation Phase
説明
A proof-of-concept $\Delta\Sigma \mathbf{AD}$ modulator using dynamic analog components with simplified operation mode is designed and fabricated in 90nm CMOS technology. The measurement results of the experimental prototype demonstrate the feasibility of the proposed modulator architecture which can guarantee the reset time for ring-amplifier and relax the speed requirement on the asynchronous SAR quantizer. The peak SNDR of 77.93dB and SNR of 84.16dB are achieved while a sinusoid −4dBFS input is sampled at 14MS/s with signal bandwidth of 109kHz. The total analog power consumption of the prototype modulator is $720\mu \mathbf{W}$ under the supply voltage of 1.2V.
収録刊行物
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- 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)
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2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) 442-446, 2018-11
IEEE
