VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes
書誌事項
- 公開日
- 2007-05
- DOI
-
- 10.1109/iscas.2007.378514
- 公開者
- IEEE
収録刊行物
-
- 2007 IEEE International Symposium on Circuits and Systems
-
2007 IEEE International Symposium on Circuits and Systems 2104-2107, 2007-05
IEEE