Data and memory optimization techniques for embedded systems

DOI Web Site 被引用文献7件
  • P. R. Panda
    Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA
  • F. Catthoor
    Inter-University Microelectronics Centre and Katholieke Universiteit Leuven, Kapeldreef 75, Leuven, Belgium
  • N. D. Dutt
    Center for Embedded Computer Systems, University of California at Irvine, Irvine, CA
  • K. Danckaert
    Inter-University Microelectronics Centre, Kapeldreef 75, Leuven, Belgium
  • E. Brockmeyer
    Inter-University Microelectronics Centre, Kapeldreef 75, Leuven, Belgium
  • C. Kulkarni
    Inter-University Microelectronics Centre, Kapeldreef 75, Leuven, Belgium
  • A. Vandercappelle
    Inter-University Microelectronics Centre, Kapeldreef 75, Leuven, Belgium
  • P. G. Kjeldsberg
    Norwegian University of Science and Technology, Trondheim, Norway

説明

<jats:p>We present a survey of the state-of-the-art techniques used in performing data and memory-related optimizations in embedded systems. The optimizations are targeted directly or indirectly at the memory subsystem, and impact one or more out of three important cost metrics: area, performance, and power dissipation of the resulting implementation.</jats:p><jats:p>We first examine architecture-independent optimizations in the form of code transoformations. We next cover a broad spectrum of optimization techniques that address memory architectures at varying levels of granularity, ranging from register files to on-chip memory, data caches, and dynamic memory (DRAM). We end with memory addressing related issues.</jats:p>

収録刊行物

被引用文献 (7)*注記

もっと見る

詳細情報 詳細情報について

問題の指摘

ページトップへ