High-performance polycrystalline silicon thin-film transistor with multiple nanowire channels and lightly doped drain structure

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  • Yung-Chun Wu
    Institute of Electronics, National Chiao Tung University, Taiwan, Republic of China
  • Ting-Chang Chang
    Department of Physics and Institute of Electro-Optical Engineering, Center for Nanoscience and Nanotechnology, National Sun Yat-Sen University, Taiwan, Republic of China
  • Chun-Yen Chang
    Institute of Electronics, National Chiao Tung University, Taiwan, Republic of China
  • Chi-Shen Chen
    Institute of Electronics, National Chiao Tung University, Taiwan, Republic of China
  • Chun-Hao Tu
    Institute of Electronics, National Chiao Tung University, Taiwan, Republic of China
  • Po-Tsun Liu
    National Nano Device Laboratory, 1001 Ta-Hsueh Rd. Hsin-Chu 300, Taiwan, Republic of China
  • Hsiao-Wen Zan
    Institute of Electro-Optical Engineering, National Chiao Tung University, Taiwan, Republic of China
  • Ya-Hsiang Tai
    Institute of Electro-Optical Engineering, National Chiao Tung University, Taiwan, Republic of China

Description

<jats:p>This investigation examines polycrystalline silicon thin-film transistors (TFTs) with multiple nanowire channels and a lightly doped drain (LDD). A device with an LDD structure exhibits low leakage current because the lateral electrical field is reduced in the drain offset region. Additionally, multiple nanowire channels can generate fewer defects in the polysilicon grain boundary and have more efficient NH3 plasma passivation than single-channel TFTs, further reducing leakage current. They exhibit superior electrical characteristics to those of single-channel TFTs, such as a higher ON/OFF current ratio (&gt;108), a better subthreshold slope of 110 mV/decade, an absence of drain-induced barrier lowering, and suppressed kink-effect. Devices with the proposed TFTs are highly promising for use in active-matrix liquid-crystal display technologies.</jats:p>

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