Interface state generation under long-term positive-bias temperature stress for a p/sup +/ poly gate MOS structure

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書誌事項

公開日
1989-09
権利情報
  • https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html
DOI
  • 10.1109/16.34236
公開者
Institute of Electrical and Electronics Engineers (IEEE)

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説明

The long-term reliability for a p/sup +/ poly gate MOS structure under low electric field bias temperature (BT) stress is studied. A significant increase in interface-state density was observed for such a structure under positive bias conditions. This phenomenon was not observed in the n/sup +/ poly gate case. The mechanism for this interface-state increase was investigated in detail. Several possible causes, such as mobile ions, excess boron concentration in the gate oxide, electron injection from the substrate, impact ionization in the gate oxide, and hole injection from the gate electrode, were considered. All of the possible causes, except hole injection, were obviated by experiments. Although hole injection current was too small to be detected, hole injection from the p/sup +/ poly gate is a possible cause, which could explain the interface-state generation under positive-bias temperature test. For a p/sup +/ poly gate in CMOS structures, care should be taken when positive bias is applied to the gate electrode. >

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