A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor
書誌事項
- 公開日
- 2008-12
- DOI
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- 10.1109/iedm.2008.4796645
- 公開者
- IEEE
説明
A novel reconfigurable logic block with SPRAM (spin-transfer torque RAM) is demonstrated. Magnetic elements of 50 times 200 nm2 in area and CMOS logic are fully integrated. Laboratory experimental results show that our reconfigurable logic block achieves 25 MHz read out operation with the magnetic resistance of 1.62 kOmega (parallel) and the MR ratio is 91.7 %.
収録刊行物
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- 2008 IEEE International Electron Devices Meeting
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2008 IEEE International Electron Devices Meeting 1-3, 2008-12
IEEE