Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video
書誌事項
- 公開日
- 2010-08
- DOI
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- 10.1109/fpl.2010.119
- 公開者
- IEEE
説明
This?paper describes an FPGA implementation which features a hardware-oriented Scale Invariant Feature Transform (SIFT) algorithm, a scalable architecture with high-speed mode and high-accuracy mode, and highly parallel datapath modules. The proposed FPGA implementation can generate a SIFT descriptor vector with 50 MHz for VGA resolution?video?(640 × 480 pixels) at 56 frames per second (fps). ?Our proposed implementation made the operating frequency and memory bandwidth a half or less than that of the conventional FPGA implementation and as a result, we achieved a system that can provide low power consumption.
収録刊行物
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- 2010 International Conference on Field Programmable Logic and Applications
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2010 International Conference on Field Programmable Logic and Applications 2010-08
IEEE