On the threshold voltage and channel conductance of polycrystalline silicon thin-film transistors

DOI PDF 被引用文献4件
  • C. A. Dimitriadis
    Department of Physics, University of Thessaloniki, 540 06 Thessaloniki, Greece
  • D. H. Tassis
    Department of Physics, University of Thessaloniki, 540 06 Thessaloniki, Greece

書誌事項

公開日
1996-04-15
DOI
  • 10.1063/1.361752
公開者
AIP Publishing

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説明

<jats:p>A model for the grain-boundary barrier height of undoped polycrystalline silicon thin-film transistors is developed based on a rodlike structure of the grains with a square cross section and a Gaussian energy distribution of the trapping states at the grain boundaries. An analytical expression for the threshold voltage is derived in terms of the distribution parameters of the grain-boundary trapping states, the grain size, and the gate oxide thickness. Comparison between the developed model and the experimental drain current versus gate voltage data has been made and excellent agreement was obtained. The key parameters affecting the threshold voltage and the channel conductance of the transistor were investigated by computer stimulation. The threshold voltage is mainly affected by the grain size and the gate oxide thickness. For the improvement of the channel conductance, besides the passivation of the grain-boundary trapping states, the increase of the grain size and mainly the scaling down of the gate oxide thickness are the key factors.</jats:p>

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