Reversible logic synthesis with Fredkin and Peres gates
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- James Donald
- Princeton University, Princeton, NJ
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- Niraj K. Jha
- Princeton University, Princeton, NJ
Description
<jats:p> Reversible logic has applications in low-power computing and quantum computing. Most reversible logic synthesis methods are tied to particular gate types, and cannot synthesize large functions. This article extends RMRLS, a reversible logic synthesis tool, to include additional gate types. While classic RMRLS can synthesize functions using NOT, CNOT, and <jats:italic>n</jats:italic> -bit Toffoli gates, our work details the inclusion of <jats:italic>n</jats:italic> -bit Fredkin and Peres gates. We find that these additional gates reduce the average gate count for three-variable functions from 6.10 to 4.56, and improve the synthesis results of many larger functions, both in terms of gate count and quantum cost. </jats:p>
Journal
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- ACM Journal on Emerging Technologies in Computing Systems
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ACM Journal on Emerging Technologies in Computing Systems 4 (1), 1-19, 2008-03
Association for Computing Machinery (ACM)
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Details 詳細情報について
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- CRID
- 1364233269829311360
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- ISSN
- 15504840
- 15504832
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- Data Source
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- Crossref