Timing Verification System for Relay Circuit Behaviors.
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- FUKUDA Mitsuko
- Power & Industrial System R&D Division, Hitachi, Ltd.
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- YAMADA Naoyuki
- Power & Industrial System R&D Division, Hitachi, Ltd.
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- TESHIMA Toshiaki
- Omika Works, Hitachi, Ltd.
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- KAN Ken'ichi
- Omika Works, Hitachi, Ltd.
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- UTSUNOMIYA Mitsugu
- Omika Works, Hitachi, Ltd.
Bibliographic Information
- Other Title
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- Timing Verification System for Relay Ci
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Abstract
<BR>A timing verification system for analogue relay circuits has been developed. The verification is performed by Time-Symbolic Logic (TSL) simulation that allows symbolic representation of the time. With representation of the relay actuation time by time-variables, TSL simulation can simulate all possible behaviors that differ with the timing of relay action. To reduce the simulation cost, the simulation technique was improved using the characteristics of the relay circuits. Users can verify the circuit behavior without preparing numerous simulation inputs or executing numerous simulation cases. <BR>The developed system was applied to the verification of actual circuits. The circuit behaviors with all the possible timings under the realistic constraints were simulated and verified. These application studies confirmed that the developed system is useful and effective.
Journal
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- Journal of Nuclear Science and Technology
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Journal of Nuclear Science and Technology 33 (6), 455-463, 1996
Atomic Energy Society of Japan
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Keywords
Details 詳細情報について
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- CRID
- 1390001204093738496
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- NII Article ID
- 10002074875
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- NII Book ID
- AA00703720
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- COI
- 1:CAS:528:DyaK28XksVyrurk%3D
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- ISSN
- 18811248
- 00223131
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- NDL BIB ID
- 4060393
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- Text Lang
- en
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- Data Source
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- JaLC
- NDL
- Crossref
- CiNii Articles
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- Abstract License Flag
- Disallowed