Effects of Address-on-Time on Wall Voltage Variation during Address-Period in AC Plasma Display Panel

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  • CHOI Byung-Tae
    School of Electrical Engineering and Computer Science, Kyungpook National University
  • PARK Hyung Dal
    School of Electrical Engineering and Computer Science, Kyungpook National University
  • TAE Heung-Sik
    School of Electrical Engineering and Computer Science, Kyungpook National University

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Abstract

To explain the variation of the address discharge during an address period, the wall voltage variation during an address period was investigated as a function of the address-on-time by using the Vt closed curves. It was observed that the wall voltage between the scan and address electrodes was decreased with an increase in the address-on-time. It was also observed that the wall voltage variation during an address period strongly depended on the voltage difference between the scan and address electrodes. Based on this result, the modified driving waveform to raise the level of Vscanw, was proposed to minimize the voltage difference between the scan and address electrodes. However, the modified driving waveform resulted in the increase in the falling time of scan pulse. Finally, the overlapped double scan waveform was proposed to reduce a falling time of scan pulse under the raised voltage level of Vscanw, also.

Journal

  • IEICE Transactions on Electronics

    IEICE Transactions on Electronics E92-C (11), 1347-1352, 2009

    The Institute of Electronics, Information and Communication Engineers

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