New Low-Voltage Low-Latency Mixed-Voltage I/O Buffer

DOI Web Site 参考文献7件
  • KIM Joung-Yeal
    School of Information and Communication Engineering, Sungkyunkwan University Samsung Electronics
  • PARK Su-Jin
    School of Information and Communication Engineering, Sungkyunkwan University Samsung Electronics
  • KIM Yong-Ki
    School of Information and Communication Engineering, Sungkyunkwan University
  • HAN Sang-Keun
    School of Information and Communication Engineering, Sungkyunkwan University Samsung Electronics
  • JUN Young-Hyun
    Samsung Electronics
  • LEE Chilgee
    School of Information and Communication Engineering, Sungkyunkwan University
  • HAN Tae Hee
    School of Information and Communication Engineering, Sungkyunkwan University
  • KONG Bai-Sun
    School of Information and Communication Engineering, Sungkyunkwan University

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説明

A new mixed-voltage I/O buffer for low-voltage low-latency operation is proposed in this paper. The proposed buffer adopts a novel delay-based timing-control scheme to efficiently avoid problems like gate-oxide stress and hot-carrier degradation. The proposed timing-control scheme also allows the buffer to have a lower latency for transmitting data by avoiding the use of timing-critical circuits like series-connected transmission gates (TGs) and triple-stacked transistors. The latency for receiving data at low supply voltage is also reduced by employing a variable stacked transistor gate-biasing scheme. Comparison results in an 80-nm CMOS process indicated that the proposed mixed-voltage I/O buffer improved up to 79.3% for receiving the external data and up to 23.8% for transmitting the internal data at a supply voltage of 1.2V.

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