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- KURATA Naruki
- Graduate School of Information Science and Technology, The University of Tokyo
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- SHIOYA Ryota
- Graduate School of Engineering, Nagoya University
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- GOSHIMA Masahiro
- National Institute of Informatics
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- SAKAI Shuichi
- Graduate School of Information Science and Technology, The University of Tokyo
説明
To eliminate CAMs from the load/store queues, several techniques to detect memory access order violation with hash filters composed of RAMs have been proposed. This paper proposes a technique with parallel counting Bloom filters (PCBF). A Bloom filter has extremely low false positive rates owing to multiple hash functions. Although some existing researches claim the use of Bloom filters, none of them make mention to multiple hash functions. This paper also addresses the problem relevant to the variety of access sizes of load/store instructions. The evaluation results show that our technique, with only 2720-bit Bloom filters, achieves a relative IPC of 99.0% while the area and power consumption are greatly reduced to 14.3% and 22.0% compared to a conventional model with CAMs. The filter is much smaller than usual branch predictors.
収録刊行物
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- IEICE Transactions on Electronics
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IEICE Transactions on Electronics E98.C (7), 580-593, 2015
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390001204378401792
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- NII論文ID
- 130005086133
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- ISSN
- 17451353
- 09168524
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
- KAKEN
- OpenAIRE
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- 抄録ライセンスフラグ
- 使用不可