High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme
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- MIYASE Kohei
- Kyushu Institute of Technology
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- WEN Xiaoqing
- Kyushu Institute of Technology
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- FURUKAWA Hiroshi
- Kyushu Institute of Technology
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- YAMATO Yuta
- Kyushu Institute of Technology
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- KAJIHARA Seiji
- Kyushu Institute of Technology
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- GIRARD Patrick
- LIRMM
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- WANG Laung-Terng
- SynTest
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- TEHRANIPOOR Mohammad
- University of Connecticut
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抄録
At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to equalize the input and output values in Stage-2of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design.
収録刊行物
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- IEICE Transactions on Information and Systems
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IEICE Transactions on Information and Systems E93-D (1), 2-9, 2010
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詳細情報 詳細情報について
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- CRID
- 1390001204378865152
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- NII論文ID
- 10026812940
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- NII書誌ID
- AA10826272
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- ISSN
- 17451361
- 09168532
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- HANDLE
- 10228/00007530
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- IRDB
- Crossref
- CiNii Articles
- KAKEN
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- 抄録ライセンスフラグ
- 使用不可