書誌事項
- タイトル別名
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- A vision chip using pulse width modulation technique
- パルス ドウサ ビジョンチップ ノ シサク
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抄録
A vision chip employing pulse width modulation(PWM) circuitry in each pixel is designed and fabricated. The neighboring pixels are interconnected with active resistors to diffuse noise, which is effective to decrease fixed pattern noise from 1% to 0.2%. By using this PWM technique it is demonstrated that histogram equalization and A/D conversion can be simultaneously realized during accumulation period. A comparator, which is used for the PWM operation, consists of one capacitor and three transistors and has A/D conversion of 7-bit precision in 2 msec. 1.2μm CMOS 2-poly 2-metal process is used to fabricate the chip, which has 16 × 16 pixels with the pixel size of 158μm × 103μm. The power consumption is 300μW per pixel in the processing speed of 500 frames per second.
収録刊行物
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- 映像情報メディア学会技術報告
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映像情報メディア学会技術報告 24.3 (0), 19-24, 2000
一般社団法人 映像情報メディア学会
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詳細情報 詳細情報について
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- CRID
- 1390001204523771392
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- NII論文ID
- 110003687786
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- NII書誌ID
- AN00348041
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- ISSN
- 02853957
- 24241970
- 13426893
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- 本文言語コード
- ja
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- データソース種別
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- JaLC
- NDL
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可