Quantitative Characterization of Substrate Noise for Physical Design Guides in Digital Circuits

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  • CMOSデジタル回路の基板雑音定量評価と低雑音化レイアウト指針
  • CMOS デジタル カイロ ノ キバン ザツオン テイリョウ ヒョウカ ト テイザツオンカ レイアウト シシン

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Abstract

Substrate noise is quantitatively evaluated by gain calibrated substrate voltage measurements in a 100 ps-100 μV resolution. Activity in a digital block is a key amount to which the noise intensity is proportional, and its reduction is a straight and universal solution to suppress the noise. Use of Kelvin grounding in the source circuits and placing a guardband proximate to the receiver circuits together also attenuates the noise significantly, however, the effect is limited to the low frequency components such as a ringing.

Journal

  • ITE Technical Report

    ITE Technical Report 24.52 (0), 1-7, 2000

    The Institute of Image Information and Television Engineers

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