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On-chip background calibration of time-interleaved ADC
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- Oshima Takashi
- Central Research Laboratory, HITACHI Ltd.
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- Takahashi Tomomi
- Central Research Laboratory, HITACHI Ltd.
Bibliographic Information
- Other Title
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- タイムインターリーブADCのオンチップバックグランド補正(アナログ,アナデジ混載,RF及びセンサインタフェース回路)
- タイムインターリーブADCのオンチップバックグランド補正
- タイムインターリーブ ADC ノ オンチップバックグランド ホセイ
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Description
An extremely-high-speed high-resolution time-interleaved ADC is a key enabler of the next-generation applications. The gain, offset and sampling-timing mismatches among unit ADCs of a time-interleaved ADC are compensated by the proposed background calibration, which is simple enough to be implemented on a single chip.
Journal
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- ITE Technical Report
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ITE Technical Report 34.29 (0), 79-84, 2010
The Institute of Image Information and Television Engineers
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Details 詳細情報について
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- CRID
- 1390001204526322944
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- NII Article ID
- 110007701345
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- NII Book ID
- AN1059086X
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- ISSN
- 24241970
- 13426893
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- NDL BIB ID
- 10810647
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- Text Lang
- ja
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- Data Source
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- JaLC
- NDL Search
- CiNii Articles
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- Abstract License Flag
- Disallowed