Chip-to-Chip Half Duplex Data Communication at 135Mbps Over Power-Supply Rails

DOI Web Site 4 References
  • HASHIDA Takushi
    Kobe University Dept. of Computer Science and Systems Engineering
  • NAGATA Makoto
    Kobe University Dept. of Computer Science and Systems Engineering

Bibliographic Information

Other Title
  • 電源線を用いた135Mbps双方向チップ間通信技術(アナログ,アナデジ混載,RF及びセンサインタフェース回路)
  • 電源線を用いた135Mbps双方向チップ間通信技術
  • デンゲンセン オ モチイタ 135Mbps ソウホウコウ チップ カン ツウシン ギジュツ

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Description

Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at 135Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by more than 30dB, purifying power supply current for internal circuits. Chip-to-chip power line communication invokes supplementary diagnosis functionality to be embedded in SoCs at the time of power connection, with the reduced cost of pin counts.

Journal

  • ITE Technical Report

    ITE Technical Report 33.39 (0), 15-18, 2009

    The Institute of Image Information and Television Engineers

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