Column parallel SS-ADC with TDC using multi-phase clock signals for CMOS imagers(Circuit technologies,2nd Asian Image Sensors and Imaging Systems Symposium)

DOI
  • Ikebe Masayuki
    Graduate School of Information Science and Technology, Hokkaido University
  • Uchida Daisuke
    Graduate School of Information Science and Technology, Hokkaido University
  • Someya Makito
    Graduate School of Information Science and Technology, Hokkaido University
  • Watanabe Kaori
    Graduate School of Information Science and Technology, Hokkaido University
  • Kinoshita Koudai
    Graduate School of Information Science and Technology, Hokkaido University
  • Chikuda Satoshi
    Graduate School of Information Science and Technology, Hokkaido University
  • Motohisa Juinichi
    Graduate School of Information Science and Technology, Hokkaido University

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Description

We propose a single-slop ADC with a time to digital converter (TDC) that uses a multi-phase clock. When the TDC with resolution of n bits is adapted to the ADC, the conversion time is reduced by a factor of 2^n. Applying the TDC that uses multi-phase-clock signal reduced the number of circuit elements, achieved consistency between the single-slope ADC and the TDC, and realized robust meta-stability.

Journal

  • ITE Technical Report

    ITE Technical Report 38.47 (0), 13-14, 2014

    The Institute of Image Information and Television Engineers

Keywords

Details 詳細情報について

  • CRID
    1390001204530397696
  • NII Article ID
    110009900468
  • DOI
    10.11485/itetr.38.47.0_13
  • ISSN
    24241970
    13426893
  • Text Lang
    en
  • Data Source
    • JaLC
    • CiNii Articles
  • Abstract License Flag
    Disallowed

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