高速デジタル回路におけるチップ部品パッド直下のグラウンドクリアランスサイズの簡易計算式の提案

DOI Web Site Web Site 参考文献10件
  • 奈良 茂夫
    富士ゼロックス株式会社研究技術開発本部システム技術研究所

書誌事項

タイトル別名
  • A Proposal of Simple Calculations for the Ground Clearance Size beneath the SMT Chip Pad on the High-Speed Digital Circuits
  • コウソク デジタル カイロ ニ オケル チップ ブヒン パッド チョッカ ノ グラウンドクリアランスサイズ ノ カンイ ケイサンシキ ノ テイアン

この論文をさがす

抄録

In recent years, PCI Express and USB have become established as high-speed serial transmission methods, reaching speeds of 5–10 Gbps and showing remarkable progress. As a result, several new design techniques for high-speed digital circuits have been recommended for printed circuit boards (PCB) by device makers. However, in order to adopt the actual designs, it is necessary to grasp their effects and detailed mechanisms. We focused on a technology which removes the copper on the ground plane beneath the chip component pad, and verified the effect. Design methods corresponding to the layer constitution and the material of the printed circuit board are proposed. The S-parameter, current distribution, and emission characteristics are analyzed by means of an electromagnetic field analysis simulator (Sonnet EM) of the method-of-moment. In addition, the S-parameter of the test board was measured and the effect was verified.

収録刊行物

参考文献 (10)*注記

もっと見る

キーワード

詳細情報 詳細情報について

問題の指摘

ページトップへ