Hardware Design and Implementation of IP-over-1394 Protocol Stack and Its Evaluation
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- Abe Kôki
- Department of Computer Science, the University of Electro-Communications
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- Hassan Mohd Yusairi Bin Abu
- Department of Computer Science, the University of Electro-Communications
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Abstract
This paper describes the hardware design of core functions of the Internet protocol IP over IEEE1394 interface (IP over 1394) and its implementation on an FPGA. The design was evaluated by counting the number of FPGA logic elements required for the implementation. Using a system clock of 49.152MHz, we verified that packets sent from an application on top of the protocol stack were correctly received by the other protocol stack via the IEEE1394 port at a transfer rate of 400 Mbps. We also verified the communication behaviors of the design with an isochronous resource manager to reserve a channel prior to data transmissions. The hardware cost of the core IP layer was less than that of the link layer. The evaluation results will help the IP-over-1394 designers explore quantitatively various spectrum of the software/hardware design alternatives.
Journal
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- IEEJ Transactions on Electronics, Information and Systems
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IEEJ Transactions on Electronics, Information and Systems 125 (3), 413-419, 2005
The Institute of Electrical Engineers of Japan
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Details 詳細情報について
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- CRID
- 1390001204605669248
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- NII Article ID
- 10014490235
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- NII Book ID
- AN10065950
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- ISSN
- 13488155
- 03854221
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- NDL BIB ID
- 7270234
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- Text Lang
- en
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- Data Source
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- JaLC
- NDL
- Crossref
- CiNii Articles
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- Abstract License Flag
- Disallowed