書誌事項
- タイトル別名
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- A Study of Self-Dithering for ΔΣ Fractional-N PLL
- DSガタ ブンスウ ブンシュウ PLL ノ セルフディザリング シュホウ ノ ケントウ
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The ΔΣ fractional-N PLL is been researched to realize a low fractional spurious signal characteristic. In this PLL, the ΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed. As a result, the limit cycle oscillation increases a spurious signal power. Therefore, some method is required for suppressing this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without the external dither generating circuit. The proposed circuit generates the dither from internal signals of PLL. We simulated the output spectrum of the proposed circuit. As a result, we show that the proposed circuit suppressed the limit cycle oscillation, and that the spurious level of the proposed circuit was almost equals to a spurious level without the limit cycle oscillation.
収録刊行物
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- 電気学会論文誌Ｃ（電子・情報・システム部門誌）
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電気学会論文誌Ｃ（電子・情報・システム部門誌） 133 (2), 234-238, 2013
一般社団法人 電気学会
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詳細情報 詳細情報について
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- CRID
- 1390001204608407808
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- NII論文ID
- 10031142430
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- NII書誌ID
- AN10065950
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- ISSN
- 13488155
- 03854221
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- NDL書誌ID
- 024280266
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- 本文言語コード
- ja
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- データソース種別
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- JaLC
- NDL
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- 抄録ライセンスフラグ
- 使用不可