Design Method for Stacked FeRAM with Oxide-Channel Transistor

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  • Sugano Koichi
    Graduation School of Electrical and Information Engineering, Shonan Institute of Technology
  • Watanabe Shigeyoshi
    Department of Information Science, Shonan Insutitute of Technology

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  • 酸化物導電膜チャネルを用いた積層型FeRAMの設計法
  • サンカブツ ドウデン マク チャネル オ モチイタ セキソウガタ FeRAM ノ セッケイホウ

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Abstract

Design method for stacked FeRAM with oxide-channel transistor has been newly proposed. Using this architecture without sacrificing the reliability of the ferro-electric thin film, both high-speed competitive DRAM and low-cost more than 1 layered Flash memory can be successfully realized. For the case of µ=20cm2/vs stacked NAND structure is available. For the case of µ=0.2cm2/vs stacked NOR structure is effective.

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