4進SD数全加算器におけるニューロンMOSFETのフローティングゲート面積の縮小

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  • The Reduction of the Floating Gate Area in the Quaternary Full Adder with the Singed Digit Number Representation using Neuron MOSFET
  • 4シン SDスウ ゼン カサンキ ニ オケル ニューロン MOSFET ノ フローティングゲート メンセキ ノ シュクショウ

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As the development of the fine fabrication technology increases a gate density, the wiring delay by the number of the entry pins and the inner wiring is becoming a serious problem. On the other hand, because it is possible to make a signal correspond to the many levels in the multiple valued logic system, the amount of information per line increases. Then, the inner wiring area and the number of the transistors can be decreased. Especially, the electric current mode has been often used in the multiple valued logic system, because it is possible to utilize the advantage that the addition and subtraction calculation can be executed by using only the wiring. However, in the electric current mode, the consumption increase of the electric power can not be ignored. Because the neuron MOSFET is manufactured in the 2 layer poly silicon CMOS process, a special manufacturing process isn't needed. When using a neuron MOSFET at the binary logic circuit, it is possible that the number of the transistors and the number of the wiring are substantially reduced. In the floating gate part of the neuron MOSFET, the electric charges are piled up and the electric charges are balanced. By using neuron MOSFET source follower for the output part in adopting this function, the multiple valued logic circuits can be composed in the voltage mode.<br> In this paper, by using a neuron MOSFET as the element of the multiple valued logic circuits, it is designing the layout of the quaternary full adder, which is due to the voltage mode, with the signed digit number representation. However, as for the layout figure of this full adder, the rate with the area of the floating gate part accounts for becomes big. And, the layout area gets widely. Therefore, by attempting to share a floating gate, it is reducing layout area. It is shown in the experiment that the occupation percentage of the floating gate is reduced to about 61%, and also to about 41% as the whole layout area, after the sharing of the floating gate.

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