A JPEG2000 Codec System Architecture for Single Tile Processing
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- MASUZAKI Takahiko
- Dept. of Communications and Computer Engineering, Kyoto University
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- TSUTSUI Hiroshi
- Dept. of Information Systems Engineering, Osaka University
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- ONOYE Takao
- Dept. of Information Systems Engineering, Osaka University
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- MIZUNO Yusuke
- MegaChips Corporation
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- SASAKI Gen
- MegaChips Corporation
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- NAKAMURA Yukihiro
- Research Organization of Science and Engineering, Ritsumeikan University
Bibliographic Information
- Other Title
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- シングルタイルJPEG2000コーデックのシステム構成
- シングルタイル JPEG 2000 コーデック ノ システム コウセイ
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Abstract
A system architecture of JPEG2000 codec LSI is developed, which is dedicated to high resolution digital images. When single-tile processing technique is employed in order to maintain image quality, the requirement for on-chip memory amount and I/O bandwidth becomes serious issue. A line-based DWT is devised for our system architecture, in which image data is processed by rectangle pieces. In addition, we introduce a scheme to calculate required system resources with varying image sizes, DWT levels, and use of intermediate data buffer so as to investigate an efficient system architecture. Based on the proposed system architecture, a JPEG2000 codec LSI, supporting 8,192×8,192 images by single-tile processing, is implemented by using 2.1M gates, which dissipates 137.1mW from 1.8V (core) power supply at 27MHz operation.
Journal
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- The Journal of the Institute of Image Electronics Engineers of Japan
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The Journal of the Institute of Image Electronics Engineers of Japan 38 (3), 296-304, 2009
The Institute of Image Electronics Engineers of Japan
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Details 詳細情報について
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- CRID
- 1390001204610424064
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- NII Article ID
- 130004437777
- 10025521940
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- NII Book ID
- AN00041650
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- ISSN
- 13480316
- 02859831
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- NDL BIB ID
- 10346759
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- Text Lang
- ja
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- Data Source
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- JaLC
- NDL
- CiNii Articles
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- Abstract License Flag
- Disallowed
