書誌事項
- タイトル別名
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- Scheduling Method of Lot Operating Sequence in Semiconductor Fabrication
- ハンドウタイ セイゾウ コウテイ ニ オケル ロット ショリ ジュンジョ ノ
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説明
This paper discusses the lot scheduling method in a semiconductor fabrication, which is a typical repetitive production process. As for the algorithm to schedule lot operating sequence, simulated annealing (SA) method is applied to this scheduling formulated in the combinatorial optimization problem between machines and silicon wafer lots. To accelerate convergence of SA computation keeping up the solution quality, a new technique for reduction of the problem size and improvement of neighborhood creation are developed. Moreover, in our system, material flow in every process is simulated to consider not only the lot inventory but also the future lot arrival.
収録刊行物
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- システム制御情報学会論文誌
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システム制御情報学会論文誌 9 (12), 573-581, 1996
一般社団法人 システム制御情報学会
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詳細情報 詳細情報について
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- CRID
- 1390001205164857600
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- NII論文ID
- 10004325090
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- NII書誌ID
- AN1013280X
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- ISSN
- 2185811X
- 13425668
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- NDL書誌ID
- 4094970
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- データソース種別
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- JaLC
- NDL
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- 抄録ライセンスフラグ
- 使用不可