Design of the ultra low-power synchronizer using ADCL buffer for adiabatic logic


The adiabatic dynamic CMOS logic (ADCL) has been studied to reduce the power dissipation in conventional CMOS logic. The clock signal of logic circuits should be synchronized with the AC power source to maintain adiabatic charging/discharging with low power for the ADCL. In this paper, an ultra low-power synchronizer using ADCL buffer is proposed. The ADCL buffer has been designed using features of automatic synchronization between AC signal and output of gate stage. Power consumptions of the proposed ADCL synchronizer are found to be 99.4nW at best case and 109.8nW at worst case, when AC signal and clock frequencies are 110MHz and 10MHz, respectively.


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