LDO regulator with high power supply rejection at 10 MHz

DOI Web Site 被引用文献2件 参考文献13件
  • Javed Khurram
    Department of Communication and Electronics Engineering, Hanyang University
  • Roh Jeongjin
    Department of Communication and Electronics Engineering, Hanyang University

この論文をさがす

説明

<p>A new high-frequency power supply rejection (PSR) improvement technique is presented for a low-dropout (LDO) regulator. The proposed technique utilizes a negative capacitance at the gate of the power transistor to enhance the PSR at high frequencies by neutralizing the effect of parasitic capacitances. The simulation results show that the LDO is able to achieve a PSR of −67.9 dB at 10 MHz.</p>

収録刊行物

  • IEICE Electronics Express

    IEICE Electronics Express 13 (24), 20160665-20160665, 2016

    一般社団法人 電子情報通信学会

被引用文献 (2)*注記

もっと見る

参考文献 (13)*注記

もっと見る

キーワード

詳細情報 詳細情報について

問題の指摘

ページトップへ