三相PWMインバータのスイッチング回数の低減法

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タイトル別名
  • Reduction Technique of Number of Switching Times in Three-Phase PWM Inverters
  • サンソウ PWM インバータ ノ スイッチング カイスウ ノ テイゲンポウ

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Reduction of switching losses of PWM inverters which are widely used is important to improve their efficiencies.This paper proposes a reduction technique of number of switching times in three-phase PWM inverters. It is based on careful selection of switching vectors in the space vector map, considering their differences which correspond to number of switching times. This is reduced to a simple rule to admit only one-phase for one switching to eliminate unnecessary switching. This rule is equivalent to a rule map among switch vectors on the space vector map. It reduced number of switching times to 2/3 in a 2-level inverter. It is a generalized form of the two-phase modulation method. Furthermore it includes the one-phase modulation method as a special case. The proposed method can be applied also to 3-level inverter.

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