A Case Study: Energy Efficient High Throughput Chip Multi-Processor Using Reduced-complexity Cores for Transaction Processing Workload

Asato Akira, Kawaba Motoyuki, Walker William, Okawara Hideki, Ando Hisashige

doi:10.2197/ipsjdc.1.204

A Case Study: Energy Efficient High Throughput Chip Multi-Processor Using Reduced-complexity Cores for Transaction Processing Workload

DOI Web Site 参考文献9件

Asato Akira

Fujitsu Laboratories Ltd., Japan
Kawaba Motoyuki

Fujitsu Laboratories Ltd., Japan
Walker William

Fujitsu Laboratories of America, USA
Okawara Hideki

Fujitsu Laboratories Ltd., Japan
Ando Hisashige

Fujitsu Limited, Japan

書誌事項

公開日: 2005

DOI

10.2197/ipsjdc.1.204

公開者: 一般社団法人情報処理学会

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説明

The pursuit of instruction-level parallelism using more transistors produces diminishing returns and also increases power dissipation of general purpose processors. This paper studies a chip multi-processor (CMP) with smaller processor cores as a means to achieve high aggregate throughput and improved energy efficiency. The benefit of this design approach increases as the number of cores on a chip increases, as enabled by semiconductor process scaling. The feasibility of a processor core 40% of the size of a baseline high performance processor that delivers about 70% of its performance is shown. The CMP populated by smaller cores to fill the same silicon area delivers 2.3 times higher performance in transaction processing represented by TPC-C benchmarks than the baseline processor scaled into the same technology. The CMP also achieves 38% higher energy efficiency.