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- Oku Shinji
- Kyushu Institute of Technology
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- Kajihara Seiji
- Kyushu Institute of Technology JST, CREST
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- Sato Yasuo
- Kyushu Institute of Technology JST, CREST
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- Miyase Kohei
- Kyushu Institute of Technology JST, CREST
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- Wen Xiaoqing
- Kyushu Institute of Technology JST, CREST
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抄録
This paper proposes a method to compute delay values in 3-valued fault simulation for test cubes which are test patterns with unspecified values (Xs). Because the detectable delay size of each fault by a test cube is not fixed before assigning logic values to the Xs in the test cube, the proposed method only computes a range of the detectable delay values of the test patterns covered by the test cubes. By using the proposed method, we derive the lowest and the highest test quality of test patterns covered by the test cubes. Furthermore, we also propose a GA (genetic algorithm)-based method to generate fully specified test patterns with high test quality from test cubes. Experimental results for benchmark circuits show the effectiveness of the proposed methods.
収録刊行物
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- Information and Media Technologies
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Information and Media Technologies 5 (4), 1147-1155, 2010
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詳細情報 詳細情報について
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- CRID
- 1390001205263700480
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- NII論文ID
- 110009599095
- 130000418476
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- NII書誌ID
- AA12394951
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- ISSN
- 18810896
- 18826687
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- HANDLE
- 10228/00007534
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- IRDB
- Crossref
- CiNii Articles
- KAKEN
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- 抄録ライセンスフラグ
- 使用不可