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- Cong Jason
- Computer Science Department, University of California, Los Angeles California NanoSystems Institute
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- Luo Guojie
- Computer Science Department, University of California, Los Angeles
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説明
The task of 3D physical design is to map a circuit from a netlist (structural) representation into a geometric (physical) representation according to a specific 3D IC technology with multiple active device layers. This paper discusses the recent progress made on the major steps in 3D physical design, including 3D floorplanning, 3D placement, 3D routing and thermal through-silicon via (TS via) planning, and outlines the challenges ahead.
収録刊行物
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- IPSJ Transactions on System LSI Design Methodology
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IPSJ Transactions on System LSI Design Methodology 3 2-18, 2010
一般社団法人 情報処理学会
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詳細情報 詳細情報について
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- CRID
- 1390001205292649216
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- NII論文ID
- 110009599074
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- NII書誌ID
- AA12394951
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- ISSN
- 18826687
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可