Hardware acceleration of a basis function network

DOI

Bibliographic Information

Other Title
  • 並列処理ハードウエアによる基底関数ネットワークの高速化

Abstract

Hardware acceleration of a basis function network which has a good spatial approximation ability is described in this paper. By using pipe-line architecture and simplifying the algorithm, high speed operation (10 times as fast as the previous model) has been achieved. We implement the proposed system to an FPGA and confirm the performance with computer simulations (delay-simulations). By comparing the previous systems, the validity of the proposed system is discussed.

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Keywords

Details 詳細情報について

  • CRID
    1390001205668224768
  • NII Article ID
    130005034984
  • DOI
    10.14864/fss.21.0.180.0
  • Data Source
    • JaLC
    • CiNii Articles
  • Abstract License Flag
    Disallowed

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