Reduction of Charge Build-Up during Reactive Ion Etching by Using Silicon-On-Insulator Structures.

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  • Arita Kiyoshi
    Center for Microelectronic Systems, Kyushu Institute of Technology,680–4 Kawazu, Iizuka, Fukuoka 820, Japan
  • Akamatsu Masashi
    Center for Microelectronic Systems, Kyushu Institute of Technology,680–4 Kawazu, Iizuka, Fukuoka 820, Japan
  • Asano Tanemasa
    Center for Microelectronic Systems, Kyushu Institute of Technology,680–4 Kawazu, Iizuka, Fukuoka 820, Japan

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  • Reduction of Charge Build-Up during Red

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The charge build-up of silicon-on-insulator (SOI) structures during reactive ion etching has been investigated. The charge build-up was evaluated by using metal/nitride/oxide/silicon (MNOS) capacitors fabricated on SOI. It has been found that the charge build-up can be drastically reduced by using SOI, while the reduction in etching rate is only 3% less than that attained using bulk Si wafers at a relatively high RF power condition. The amount of charge build-up has been found to decrease the thickness of the buried oxide layer increases. A model to explain these phenomena is discussed.

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