Memory Operation of Silicon Quantum-Dot Floating-Gate Metal-Oxide-Semiconductor Field-Effect Transistors.

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  • Kohno Atsushi
    Department of Electrical Engineering, Hiroshima University, 1-4-1 Kagamiyama, Higashi-Hiroshima 739-8527, Japan
  • Murakami Hideki
    Department of Electrical Engineering, Hiroshima University, 1-4-1 Kagamiyama, Higashi-Hiroshima 739-8527, Japan
  • Ikeda Mitsuhisa
    Department of Electrical Engineering, Hiroshima University, 1-4-1 Kagamiyama, Higashi-Hiroshima 739-8527, Japan
  • Miyazaki Seiichi
    Department of Electrical Engineering, Hiroshima University, 1-4-1 Kagamiyama, Higashi-Hiroshima 739-8527, Japan
  • Hirose Masataka
    Department of Electrical Engineering, Hiroshima University, 1-4-1 Kagamiyama, Higashi-Hiroshima 739-8527, Japan

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Description

The drain current versus gate voltage characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs) with a silicon quantum-dot (QD) layer floating gate have shown the unique hysteresis and current bumps which arise from the electron charging or discharging of the QDs with an average dot height of 5 nm. The drain current response to application of a single-pulse gate bias has revealed that the multiple-step charging of the QD layer occurs until single electron occupation at each QD is achieved.

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