A Dual-Gate Complementary Metal-Oxide-Semiconductor Technology with Novel Self-Aligned Pocket Implantation which Takes Advantage of Elevated Source/Drain Configurations.
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- Sugihara Kohei
- Advanced Technology R&D Center, Mitsubishi Electric Corporation, 4-1 Mizuhara, Itami, Hyogo 664-8641, Japan
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- Miura Naruhisa
- Advanced Technology R&D Center, Mitsubishi Electric Corporation, 4-1 Mizuhara, Itami, Hyogo 664-8641, Japan
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- Furukawa Taisuke
- Advanced Technology R&D Center, Mitsubishi Electric Corporation, 4-1 Mizuhara, Itami, Hyogo 664-8641, Japan
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- Nakahata Takumi
- Advanced Technology R&D Center, Mitsubishi Electric Corporation, 4-1 Mizuhara, Itami, Hyogo 664-8641, Japan
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- Oishi Toshiyuki
- Advanced Technology R&D Center, Mitsubishi Electric Corporation, 4-1 Mizuhara, Itami, Hyogo 664-8641, Japan
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- Maruno Shigemitsu
- Advanced Technology R&D Center, Mitsubishi Electric Corporation, 4-1 Mizuhara, Itami, Hyogo 664-8641, Japan
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- Abe Yuji
- Advanced Technology R&D Center, Mitsubishi Electric Corporation, 4-1 Mizuhara, Itami, Hyogo 664-8641, Japan
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- Tokuda Yasunori
- Advanced Technology R&D Center, Mitsubishi Electric Corporation, 4-1 Mizuhara, Itami, Hyogo 664-8641, Japan
書誌事項
- タイトル別名
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- Dual Gate Complementary Metal Oxide Semiconductor Technology with Novel Self Aligned Pocket Implantation which Takes Advantage of Elevated Source Drain Configurations
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抄録
A dual-gate complementary metal-oxide-semiconductor technology with novel self-aligned pocket implantation is demonstrated which takes advantage of the elevated source/drain (S/D) configurations. Using the present procedure, S/D junction capacitance and leakage current were significantly suppressed for p-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) as well as for n-channel MOSFETs without degradation of the short channel characteristics. These results are interpreted in terms of the fact that the pocket impurity profiles shift to the upper positions in the deep S/D regions, though the impurity distribution at the gate edges was hardly varied. Furthermore, the suppression effects were more marked for a higher pocket implantation dosage, which will be required to suppress the short channel effects in future MOSFETs. In addition, improvement of drivability due to the reduction of the parasitic S/D resistance, an original benefit of the elevated S/D engineering, is maintained by the present technique. The present self-aligned pocket procedure is very promising as a key technology beyond the 0.1 μm node.
収録刊行物
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- Japanese Journal of Applied Physics
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Japanese Journal of Applied Physics 40 (4B), 2611-2615, 2001
The Japan Society of Applied Physics
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詳細情報 詳細情報について
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- CRID
- 1390001206253344128
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- NII論文ID
- 210000049334
- 10006619000
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- NII書誌ID
- AA10457675
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- ISSN
- 13474065
- 00214922
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- NDL書誌ID
- 5781548
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- NDL
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- 使用不可