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- CHEN Zhixiang
- Graduate School of Information, Production and Systems, Waseda University
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- PENG Xiao
- Graduate School of Information, Production and Systems, Waseda University
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- ZHAO Xiongxin
- Graduate School of Information, Production and Systems, Waseda University
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- OKAMURA Leona
- Graduate School of Information, Production and Systems, Waseda University
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- ZHOU Dajiang
- Graduate School of Information, Production and Systems, Waseda University
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- GOTO Satoshi
- Graduate School of Information, Production and Systems, Waseda University
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説明
In this paper, we introduce an LDPC decoder design for decoding a length-672 multi-rate code adopted in IEEE 802.15.3c standard. The proposed decoder features high performances in both data rate and power efficiency. A macro-layer level fully parallel layered decoding architecture is proposed to support the throughput requirement in the standard. For the proposed decoder, it takes only 4 clock cycles to process one decoding iteration. While parallelism increases, the chip routing congestion problem becomes more severe because a more complicated interconnection network is needed for message passing during the decoding process. This problem is nicely solved by our proposed efficient message permutation scheme utilizing exploited parity check matrix features. The proposed message permutation network features high compatibility and zero-logic-gate VLSI implementation, which contribute to the remarkable improvements in both area utilization ratio and total gate count. Meanwhile, frame-level pipeline decoding is applied in the design to shorten the critical path. To verify the above techniques, the proposed decoder is implemented on a chip fabricated using Fujitsu 65nm 1P12L LVT CMOS process. The chip occupies a core area of 1.30mm2 with area utilization ratio 86.3%. According to the measurement results, working at 1.2V, 400MHz and 10 iterations the proposed decoder delivers a 6.72Gb/s data throughput and dissipates a power of 537.6mW, resulting in an energy efficiency 8.0pJ/bit/iteration. Moreover, a decoder of the same architecture but with no pipeline stage for low-profile application is also implemented and evaluated at post-layout level.
収録刊行物
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- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E94-A (12), 2587-2596, 2011
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390001206311465088
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- NII論文ID
- 10030533698
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- NII書誌ID
- AA10826239
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- ISSN
- 17451337
- 09168508
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- 本文言語コード
- en
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- 資料種別
- journal article
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- データソース種別
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- JaLC
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- 抄録ライセンスフラグ
- 使用不可