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- 沼田 敏典
- (株)東芝 研究開発センター LSI基盤技術ラボラトリー
書誌事項
- タイトル別名
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- Si nanowire MOSFETs Techniques for High Performance and Low Power LSIs
- コウセイノウ ・ テイショウヒ デンリョク Si ナノワイヤトランジスタ ギジュツ
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説明
In this work, we demonstrate high-performance silicon tri-gate nanowire transistor (NW Tr.) with NW width less than 15 nm. We successfully reduced the parasitic resistance of NW Tr. by raised source/drain extensions with thin spacers with < 10 nm. Furthermore, we introduced stress memorization technique (SMT) to NW Tr. And much larger mobility increase is obtained in NW Tr. than in planar Tr. The threshold voltage variability of NW Tr. is studied and the threshold voltage variability in NW Tr. is reduced compared to planar SOI Tr. due to gate grain alignment. The performance of NW Tr. CMOS circuits under the low voltage operation is investigated by using the Spice model parameters extracted from the measurement data. The operation voltage of NW CMOS inverter is reduced smaller than that of bulk CMOS due to the ideal sub-threshold slope. NW Tr. is highly promising for the ultra-low power and high-performance LSI applications.
収録刊行物
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- 表面科学
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表面科学 33 (11), 616-621, 2012
公益社団法人 日本表面科学会
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詳細情報 詳細情報について
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- CRID
- 1390001206458977920
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- NII論文ID
- 130004486715
- 10031131001
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- NII書誌ID
- AN00334149
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- ISSN
- 18814743
- 03885321
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- NDL書誌ID
- 024089400
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- 本文言語コード
- ja
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- データソース種別
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- JaLC
- NDL
- Crossref
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- 抄録ライセンスフラグ
- 使用不可
