書誌事項
- タイトル別名
-
- Experimental Implementation of Fault Tolerance Using Dynamic Partial Reconfiguration on Xilinx Zynq-7000 SoC
- ドウテキ ブブン サイコウセイ オ モチイタ タイコショウカ シュホウ ノ Xilinx Zynq-7000 SoC ニ ヨル シサク
この論文をさがす
抄録
<p>In our previous paper, the authors proposed a fault tolerant system that adopts field programmable gate arrays (FPGA) with dynamic partial reconfiguration (DPR), based on autonomous control of reconfiguration. This study presents an experimental implementation of the proposed system that utilizes the DPR feature of Xilinx Zynq-7000 SoC. The control logic of DPR is implemented as a Linux software on the embedded ARM processor of Zynq-7000. DPR is invoked via PCAP, which is the dedicated interface for the embedded ARM processor. Four tiles (reconfigurable areas) are prepared and dynamically reconfigured to avoid the firm error of SRAM-type FPGAs. An experimental fault-tolerant system with triple redundancy and logic roving is implemented, and the measurement results of the reconfiguration time and data transfer time are presented.</p>
収録刊行物
-
- 電気学会論文誌D(産業応用部門誌)
-
電気学会論文誌D(産業応用部門誌) 141 (2), 93-99, 2021-02-01
一般社団法人 電気学会
- Tweet
キーワード
詳細情報 詳細情報について
-
- CRID
- 1390005506404144768
-
- NII論文ID
- 130007979756
-
- NII書誌ID
- AN10012320
-
- ISSN
- 13488163
- 09136339
-
- NDL書誌ID
- 031285917
-
- 本文言語コード
- ja
-
- データソース種別
-
- JaLC
- NDL
- Crossref
- CiNii Articles
- KAKEN
-
- 抄録ライセンスフラグ
- 使用不可