CubeSim: A Cycle Accurate Simulator for Multicore System with 3D SiP

In recent years, various kinds of functions, performance, and interfaces are required for IoT devices and embedded devices. From the viewpoint of an implementation cost, a single SoC (System On a Chip) is not suitable for these demands. Therefore, SiP (System In a Package) with a 3D-IC technology is expected to be an alternative solution. Especially, TCI (Thru-Chip Interface), the inter-chip wireless communication technology, has an advantage of a low cost for stacking. The host processor connected with power-efficient accelerator cores by the TCI can provide a wide range of systems according to the user's demands. When we evaluate such a system's performance, an RTL simulation using a hardware description language such as Verilog takes a long time. Thus, it is not easy to optimize the design of the stacked accelerators and the entire system. Besides, the time-consuming RTL simulation suffers from less capability of application debugging. Therefore, this work develops a cycle-accurate simulator CubeSim for the stacking system based on a MIPS R3000 compatible host processor. It enables design-space exploration by parameterizing cache size, external memory and bus latency, bus width, etc. Also, CubeSim provides an abstract class for stacked accelerators. Thereby, architects can evaluate an emerging accelerator with the host processor by defining at least cycle-level behavior of it. As a result of the evaluation, CubeSim can run the simulation up to 234 times faster than the commercial RTL simulator. In addition, two types of real chip accelerators are installed in CubeSim, and their performance is evaluated. Then, the design-space exploration shows around 38% of energy-saving at maximum.