A Hardware-Oriented Random Number Generation Method and A Verification System for FPGA

DOI オープンアクセス
  • Hori Sansei
    Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology
  • Tamukoh Hakaru
    Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology

説明

Deep learning technology has made remarkable progress in recent years and has been applied to a variety of applications such as smartphones and cloud servers. These systems employ dedicated processors to save power consumptions and process massive data. In this paper, we introduce a hardware-oriented restricted Boltzmann machine and propose a field-programmable gate array (FPGA) infrastructure for easy verification of user circuits. The infrastructure makes it easy to communicate and control between the host PC and the user circuit.

収録刊行物

キーワード

詳細情報 詳細情報について

  • CRID
    1390006750774987264
  • DOI
    10.5954/icarob.2021.os19-3
  • ISSN
    21887829
  • 本文言語コード
    en
  • データソース種別
    • JaLC
    • Crossref
    • OpenAIRE
  • 抄録ライセンスフラグ
    使用不可

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