Self-forming barriers in large-scale integrated circuits

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  • KOIKE Junichi
    Department of Materials Science, Graduate School of Engineering Tohoku University

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Other Title
  • 集積回路配線における自己形成バリヤ層
  • シュウセキ カイロ ハイセン ニ オケル ジコ ケイセイ バリヤソウ

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Abstract

<p>Multilayer interconnections of integrated circuits are composed of Cu, an SiO2-based dielectric, with liner/barrier layers between them. With continuous device scaling, line resistivity increases rapidly because of the presence of the liner/barrier. As a possible solution, we developed a self-forming barrier layer using a Cu-Mn alloy. This paper explains the underlying physical concepts to find a proper alloying element for the self-forming barrier, its chemical composition, and the formation mechanisms. Furthermore, the properties and reliability of dual-damascene lines at a 90 nm technology node are explained in comparison with the lines made with conventional materials.</p>

Journal

  • Oyo Buturi

    Oyo Buturi 90 (10), 600-609, 2021-10-05

    The Japan Society of Applied Physics

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