Acceleration of DPDK Application by Utilizing FPGA

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  • FPGAを用いたDPDKアプリケーションの高速化

Abstract

We are researching on acceleration of SPP (Soft Patch Panel), which is high-speed DPDK (Data Plane Development Kit) software connecting virtual instances with physical NICs or other virtual instances. In this research, SPP's bottleneck is evaluated, which leads scale out architecture with FPGA (Field Programmable Gate Array) based load balancer. Then, FPGA is implemented based on the architecture. Integration test reveals that the performance gets 4 times higher at 256byte or smaller packet size, and gets over 40Gbps at 256byte or bigger packet size. On the other hand, two practical problems arise: large number of CPU cores used and poor NIC scalability. The architecture improvement leads estimation that about 69% CPU cores can be reduced, and PoC evaluation shows scalability at short packet.

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